A cell array scheme of a semiconductor memory device is an important technology determining a specification of the device, together with a structure of a semiconductor layer and a process condition. The semiconductor memory device of such a cell array scheme has a stack-type gate structure, and shares a line contact with electrode lines in a plurality of cells, thereby making it possible to realize high integration. Also, since it is possible to connect in parallel and layer the electrode lines and the contact, it may implement a high function of the device.
However, the semiconductor memory device of the cell array scheme has a problem that wiring density becomes high, and it is difficult to secure an accurate process margin so that yield is deteriorated. Particularly, in a case where a sufficient process margin is not secured in a distance between the contact and a gate line, the yield may be largely deteriorated. However, in this aspect, a study on the process margin is not sufficient, for example, a probe test cannot be performed.